Benchmarks
Every number below is a modelled estimate from memory bandwidth and quantized weight size — we will not print a measured figure we did not receive. Real runs from real Macs replace estimates as they arrive.
| Chip | GB/s | Llama 3.2 3B Instruct | Qwen3 4B | Mistral 7B Instruct v0.3 | Qwen2.5 7B Instruct | InternVL3 8B |
|---|---|---|---|---|---|---|
| M1 | 68 | 7.6 | 11.5 | 6.3 | 3.2 | 5.8 |
| M1 Pro | 200 | 23.7 | 35.8 | 19.6 | 10.0 | 17.9 |
| M1 Max | 400 | 49.2 | 74.4 | 40.7 | 20.8 | 37.2 |
| M1 Ultra | 800 | 101 | 152 | 83.5 | 42.6 | 76.2 |
| M2 | 100 | 11.4 | 17.2 | 9.4 | 4.8 | 8.6 |
| M2 Pro | 200 | 24.0 | 36.2 | 19.9 | 10.1 | 18.1 |
| M2 Max | 400 | 49.8 | 75.3 | 41.3 | 21.1 | 37.6 |
| M2 Ultra | 800 | 102 | 154 | 84.6 | 43.2 | 77.2 |
| M3 | 100 | 11.4 | 17.2 | 9.4 | 4.8 | 8.6 |
| M3 Pro | 150 | 17.5 | 26.5 | 14.5 | 7.4 | 13.2 |
| M3 Max (14-core CPU) | 300 | 36.4 | 55.1 | 30.2 | 15.4 | 27.5 |
| M3 Max (16-core CPU) | 400 | 49.8 | 75.3 | 41.3 | 21.1 | 37.6 |
| M3 Ultra | 819 | 106 | 160 | 87.6 | 44.7 | 80.0 |
| M4 | 120 | 13.8 | 20.9 | 11.4 | 5.8 | 10.4 |
| M4 Pro | 273 | 33.2 | 50.1 | 27.5 | 14.0 | 25.1 |
| M4 Max (14-core CPU) | 410 | 51.7 | 78.1 | 42.8 | 21.8 | 39.1 |
| M4 Max (16-core CPU) | 546 | 69.7 | 105 | 57.7 | 29.5 | 52.7 |
| M5 | 153 | 17.9 | 27.0 | 14.8 | 7.5 | 13.5 |
| M5 Prounverified | 307 | 37.8 | 57.1 | 31.3 | 16.0 | 28.5 |
| M5 Maxunverified | 614 | 79.4 | 120 | 65.7 | 33.5 | 60.0 |
All figures marked est. — estimates derived from published bandwidth, assuming a warm model, short prompt and no thermal throttling. Expect real Macs to land within roughly ±25%.
Measured runs from real Macs
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How we would verify a submission
- Same model repo, same quantization, same runtime version.
- Warm start: the model already resident, so the first load is not counted.
- At least 256 generated tokens, reported as the median of three runs.
- No other heavy applications open, and the machine on mains power.
- Three independent submissions within 15% of each other before a number stops being labelled unverified.